The inventive concept relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a semiconductor device using a silicidation process.
As the degree of semiconductor device integration increases, a design rule becomes more strict, and the critical dimension (CD) is reduced. As a result, in semiconductor devices, because of reduced wiring and contact size, increases in wiring resistance and contact resistance become more significant. An increase in wiring resistance and contact resistance can lower semiconductor device performance. In order to reduce wiring resistance and contact resistance, a method of forming a silicide layer on gate electrodes and source/drain regions of semiconductor devices using self-alignment may be used.
In particular, in a full silicide (FUSI) layer, a gate poly oxide (GPox) process is not greatly restricted due to oxidation compared to other metal layers. Device reliability can be prevented from being lowered due to an etch byproduct formed of a high-k dielectric material.